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Digital-to-analog converter (DAC)
Figure 43. DAC channel block diagram
T S ELx[2:0] b it s
S WTR IGx
DAC control regi s ter
RM0008
TIM2_T RGO
TIM4_T RGO
TIM5_T RGO
TIM6_T RGO
TIM7_T RGO
DMAENx
EXTI_9
TIM 8 _T RGO (1)
DM A re q u e s tx
DHRx
12- b it
Control logicx
tri a nglex
LF S Rx
TENx
MAMPx[ 3 :0] b it s
WAVENx[1:0] b it s
12- b it
DORx
12- b it
V DDA
V SS A
Digit a l-to- a n a log
converterx
DAC_ OU Tx
V R EF+
a i1470 8 c
1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO .
Table 68.
DAC pins
Name
Signal type
Remarks
V REF+
Input, analog reference The higher/positive reference voltage for the DAC,
positive 2.4 V ? V REF + ? V DDA (3.3 V)
V DDA
V SSA
DAC_OUTx
Input, analog supply
Input, analog supply
ground
Analog output signal
Analog power supply
Ground for analog power supply
DAC channelx analog output
Note:
234/995
Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).
Doc ID 13902 Rev 9
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